Generally, processing speed of a processor (for example, a central processing unit (CPU)) and a hardware engine (HWE) is higher than data supply speed of a main memory such as a DRAM. Therefore, there may be a case where a cache memory to make up for the performance difference is used.
As the cache memory, an SRAM or the like faster than the main memory is used, and data on the main memory is temporarily stored in the cache memory.
If the cache memory does not exist, the processor acquires data corresponding to a data size to be accessed at a time (for example 4 bytes) from the main memory. If the cache memory exists but there is not data on a data array of the cache memory, the cache memory acquires data with a line size larger than the data size to be accessed (for example, 256 bytes) from the main memory.
On the other hand, if the requested data exists in the cache memory, the cache memory can return the data to the processor from the cache memory without acquiring the data from the main memory. Therefore, the processor or the hardware engine can access data at a high speed.
Since capacity of implementation of the cache memory is limited, it has been conventionally proposed to compress to store data. The cache memory is operated in line sizes. When handing over data to the processor, the compression cache memory extends a cache line including the requested data and returns the requested data from the cache line.
In a conventional compression cache memory, a size of a tag memory is a fixed-length size, and the number of pieces of tag data corresponding to the number of ways is stored in the tag memory. However, though a size of each piece of data is compressed and reduced, the size may be reduced more than an assumed compression ratio depending on a value of the data.
In the conventional compression cache memory, even if data is compressed at a ratio higher than an assumed compression ratio, and there is room in a data memory, the free space cannot be used as a data storage area.